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OR ED F END EL7554 M M EE EC O S Data Sheet OT R N
D N EW
ESIG
NS
EL7563
May 13, 2005 FN7296.2
Monolithic 4 Amp DC/DC Step-Down Regulator
The EL7563 is an integrated, full-featured synchronous stepdown regulator with output voltage adjustable from 1.0V to 2.5V. It is capable of delivering 4A continuous current at up to 95% efficiency. The EL7563 operates at a constant frequency pulse width modulation (PWM) mode, making external synchronization possible. Patented on-chip resistorless current sensing enables current mode control, which provides cycle-by-cycle current limiting, over-current protection, and excellent step load response. The EL7563 features power tracking, which makes the start-up sequencing of multiple converters possible. A junction temperature indicator conveniently monitors the silicon die temperature, saving the designer time on the tedious thermal characterization. The minimal external components and full functionality make this EL7563 ideal for desktop and portable applications. The EL7563 is offered in 20-pin SO and 28-pin HTSSOP packages.
Features
* Integrated synchronous MOSFETs and current mode controller * 4A continuous output current * Up to 95% efficiency * Internal patented current sense * Cycle-by-cycle current limit * 3V to 3.6V input voltage * Adjustable output voltage 1V to 2.5V * Precision reference * 0.5% load and line regulation * Adjustable switching frequency to 1MHz * Oscillator synchronization possible * Internal soft-start * Over-voltage protection * Junction temperature indicator * Over-temperature protection
Pinout
EL7563 (20-PIN SO) TOP VIEW
* Under-voltage lockout * Multiple supply start-up tracking * Power-good indicator
C5 1 VREF 0.1F C4 3 COSC R4 C3 22 0.22F 390pF C2 2.2nF 6 PGND VIN 3.3V C1 330F 7 PGND 8 VIN 9 STP 10 STN LX 15 LX 14 PGND 13 PGND 12 PGND 11 C7 330F 4 VDD 5 VTJ VDRV 17 VHI 16 C6 0.22F L1 4.7H C10 2.2nF D1 D3 C9 0.1F VOUT R2 1.58k R1 1k 2.5V 4A PG 18 D2 D4 C8 0.22F 2 SGND EN 20 FB 19
* 20-pin SO (0.300") package * 28-pin HTSSOP package * Pb-Free available (RoHS compliant)
Applications
* DSP, CPU core, and I/O supplies * Logic/Bus supplies * Portable equipment * DC/DC converter modules * GTL + Bus power supply
Typical Application Diagrams continued on page 3 Manufactured Under U.S. Patent No. 5,7323,974
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7563 Ordering Information
PART NUMBER EL7563CM EL7563CMZ (See Note) EL7563CMZ-T13 (See Note) EL7563CRE EL7563CRE-T7 EL7563CRE-T13 EL7563CREZ (See Note) EL7563CREZ-T7 (See Note) EL7563CREZ-T13 (See Note) PACKAGE 20-Pin SO (0.300") 20-Pin SO (0.300") (Pb-free) 20-Pin SO (0.300") (Pb-free) 28-Pin HTSSOP 28-Pin HTSSOP 28-Pin HTSSOP 28-Pin HTSSOP (Pb-free) 28-Pin HTSSOP (Pb-free) 28-Pin HTSSOP (Pb-free) TAPE & REEL 13" 7" 13" 7" 13" PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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EL7563
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VIN or VDD and GND . . . . . . . . . . . . +4.5V VLX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN +0.3V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VDD +0.3V VHI Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VLX +6V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Ambient Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VREF VREFTC VREFLOAD VRAMP IOSC_CHG IOSC_DIS IVDD+VDRV IVDD_OFF VDD_OFF VDD_ON TOT THYS ILEAK ILMAX RDSON RDSONTC ISTP ISTN VPGP VPGN VPG_HI VPG_LO VOVP VFB VFB_LINE VFB_LOAD VFB_TC IFB VEN_HI VEN_LO IEN
VDD = VIN = 3.3V, TA = TJ = 25C, COSC = 390pF, unless otherwise specified. CONDITIONS MIN 1.24 TYP 1.26 50 0 < IREF < 50A -1 1.15 0.1V < VOSC < 1.25V 0.1V < VOSC < 1.25V VEN = 2.7V, FOSC = 120kHz EN = 0 2.4 2.6 135 20 EN = 0, LX = 3.3V (low FET), LX = 0V (high FET) 5 Wafer level test only 30 0.2 VSTP = VIN/2 VSTN = VIN/2 With respect to target output voltage With respect to target output voltage IPG = 1mA IPG = -1mA 10 ILOAD = 0A VIN = 3.3V, VIN = 10%, ILOAD = 0A 0.5A < ILOAD < 4A -40C < TA < 85C, ILOAD = 2A VFB = 0V 0.977 0.992 0.5 0.5 1 100 200 2.7 1 VEN = 0 -4 -2.5 1.007 6 -16 2.7 0.5 -4 2.5 2.5 4 16 -6 60 10 2 200 8 5.5 1 6.5 1.5 2.65 2.95 MAX 1.28 UNIT V ppm/C % V A mA mA mA V V C C A A m m/C A A % % V V % V % % % nA V V A
DESCRIPTION Reference Accuracy Reference Temperature Coefficient Reference Load Regulation Oscillator Ramp Amplitude Oscillator Charge Current Oscillator Discharge Current VDD+VDRV Supply Current VDD Standby Current VDD for Shutdown VDD for Startup Over Temperature Threshold Over Temperature Hysteresis Internal FET Leakage Current Peak Current Limit FET On Resistance RDSON Tempco Auxiliary Supply Tracking Positive Input Pull Down Current Auxiliary Supply Tracking Negative Input Pull Up Current Positive Power Good Threshold Negative Power Good Threshold Power Good Drive High Power Good Drive Low Over Voltage Protection Output Initial Accuracy Output Line Regulation Output Load Regulation Output Temperature Stability Feedback Input Pull Up Current EN Input High Level EN Input Low Level Enable Pull Up Current
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EL7563
Closed-Loop AC Electrical Specifications
PARAMETER FOSC tSYNC MSS tBRM tLEB DMAX DESCRIPTION Oscillator Initial Accuracy Minimum Oscillator Sync Width Soft Start Slope FET Break Before Make Delay High Side FET Minimum On Time Maximum Duty Cycle (Continued) VS = VIN = 3.3V, TA = TJ = 25C, COSC = 390pF, unless otherwise specified. CONDITIONS MIN 310 TYP 365 25 0.5 15 150 95 MAX 420 UNIT kHz ns V/ms ns ns %
Typical Application Diagrams
C5 1 VREF 0.1F 2 SGND C4 3 COSC R4 22 C3 0.22F 390pF 4 VDD C2 5 VTJ 2.2nF 6 PGND VIN 3.3V C1 330F 7 PGND 8 PGND 9 PGND 10 VIN 11 VIN 12 NC 13 STP 14 STN LX 23 LX 22 LX 21 LX 20 LX 19 LX 18 NC 17 PGND 16 PGND 15 VHI 24 C6 0.22F L1 4.7H C10 2.2nF C7 330F D1 VDRV 25 D3 C9 0.1F VOUT 2.5V 4A R2 1.58k R1 1k PG 26 D2 D4 C8 0.22F FB 27 EN 28
28-PIN HTSSOP
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EL7563 Pin Descriptions
20-PIN SO (0.300") 1 2 3 4 5 6, 7 8 9 10 11, 12, 13 14, 15 16 17 18 19 20 28-PIN HTSSOP 1 2 3 4 5 6, 7, 8, 9 10, 11 13 14 15, 16 18, 19, 20, 21, 22, 23 24 25 26 27 28 PIN NAME VREF SGND COSC VDD VTJ PGND VIN STP STN PGND LX VHI VDRV PG FB EN PIN FUNCTION Bandgap reference bypass capacitor; typically 0.1F to SGND Control circuit negative supply or signal ground Oscillator timing capacitor (see performance curves) Control circuit positive supply; normally connected to VIN through an RC filter Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET Power supply input of the regulator; connected to the drain of the high-side NMOS power FET Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open for stand alone operation; 2A internal pull down current Auxiliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for stand alone operation; 2A internal pull up current Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET Inductor drive pin; high current output whose average voltage equals the regulator output voltage Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22F capacitor Positive supply of low-side driver and input voltage for high side boot strap Power good window comparator output; logic 1 when regulator output is within 10% of target output voltage Voltage feedback input; connected to external resistor divider between VOUT and SGND; a 125nA pull-up current forces VOUT to SGND in the event that FB is floating Chip enable, active high; a 2A internal pull up current enables the device if the pin is left open; a capacitor can be added at this pin to delay the start of converter
Typical Performance Curves (20 Pin SO Package)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
VIN=3.3V 100 95 EFFICIENCY (%) 90 85 80 75 70 VO=1.2V VO=1V 0 0.5 1 1.5 2 2.5 3 3.5 4 VO=2.5V VO=1.8V EFFICIENCY (%) 100 95 90 85 80 75 70 65 60 0.1 0.6 1.1 1.6 2.1 IO (A) 2.6 3.1 3.6 4 VO=1.8V VO=1.2V VO=2.5V VIN=3.3V
LOAD CURRENT IO (A)
FIGURE 1. EL7563CM EFFICIENCY vs IO
FIGURE 2. EL7563CRE EFFICIENCY
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EL7563 Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
VIN=3.3V 1.8 1.6 1.4 POWER LOSS (W) 1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VO=2.5V VO=1V VO=1.2V PLOSS (W) VO=1.8V 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 IO (A) 3 4 VO=1.2V VO=2.5V
OUTPUT CURRENT IO (A)
FIGURE 3. EL7563CM CONVERTER POWER LOSS vs IO
VO=2.5V VIN=3.6V
FIGURE 4. EL7563CRE TOTAL CONVERTER POWER LOSS
2.505 2.5 OUTPUT VOLTAGE (V) 2.495
0.6 0.4 0.2 VO (V) (%) VIN=3.3V 0 -0.2 -0.4 -0.6
VO=2.5V
VIN=3.3V VIN=3.6V
2.49 2.485 2.48 2.475 2.47 2.465 0.5 1 1.5 2 2.5 3 VIN=3V
VIN=3V
3.5
4
-0.8
0
0.5
1
1.5
2 IO (A)
2.5
3
3.5
4
LOAD CURRENT IO (A)
FIGURE 5. EL7563CM LOAD REGULATION
FIGURE 6. EL7563CRE LOAD REGULATION
50 THERMAL RESISTANCE (C/W) 46 42 38
TEST CONDITION: CHIP IN THE CENTER OF COPPER AREA
50 45 JA (C/W) 40 35 30
CONDITION: EL7563CRE THERMAL PAD SOLDERED TO 2-LAYER PCB WITH 0.039" THICKNESS AND 1 OZ. COPPER ON BOTH SIDES
WITH NO AIRFLOW
WITH 100 LFPM AIRFLOW 34 30 1 OZ. COPPER PCB USED 1 1.5 2 2.5 3 3.5 4
25
0
1.5
2
2.5
3
3.5
4
PCB COPPER HEAT-SINKING AREA (in2)
PCB AREA (in2)
FIGURE 7. EL7563CM JA vs COPPER AREA
FIGURE 8. EL7563CRE THERMAL RESISTANCE vs PCB AREA - NO AIR FLOW
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FN7296.2 May 13, 2005
EL7563 Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
JUNCTION TEMPERATURE RISE (C)
60 50 40 30 20 10 0 500 LPF 0 1 2 IO (A) 3 4 NO AIRFLOW TJ RISE 200 LFM 100 LFM
45 40 35 30 25 20 15 10 5 0 1 1.5 2 2.5 IO (A) 3 3.5 4
FIGURE 9. EL7563CM JUNCTION TEMPERATURE RISE ON DEMO BOARD
FIGURE 10. EL7563CRE JUNCTION TEMPERATURE RISE ON DEMO BOARD - NO AIR FLOW
360 OSCILLATOR FREQUENCY (kHz) 350 340 330 320 310 300 290 280 -40 -20 0 20 40 60 80 IO=0A IO=4A FS (kHz)
1000 900 800 700 600 500 400 300 200 100 100 200 300 400 500 600 700 800 900 1000
TEMPERATURE (C)
COSC (pF)
FIGURE 11. SWITCHING FREQUENCY vs TEMPERATURE
FIGURE 12. SWITCHING FREQUENCY vs COSC
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1.5
7 VIN=3.6V VIN=3V VIN=3.3V VTJ 1.1 4 0.9 -20 0 20 40 TJ (C) 60 80 100 120 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (C) 1.3
ILMT (A)
6
5
3 -40
FIGURE 13. CURRENT LIMIT vs TJ
FIGURE 14. VTJ vs JUNCTION TEMPERATURE
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FN7296.2 May 13, 2005
EL7563 Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
VIN=3.3V, VO=1.8V, IO=4A VIN VLX IO iL VO VO
VIN=3.3V, VO=1.8V, IO=0.2A-4A
FIGURE 15. SWITCHING WAVEFORMS
FIGURE 16. TRANSIENT RESPONSE
VIN=3.3V, VO=1.8V, IO=0.2A VIN
VIN=3.3V, VO=1.8V, IO=4A
VO
FIGURE 17. POWER-UP
FIGURE 18. POWER-DOWN
VIN=3.3V, VO=1.8V AT 4A EN
VIN=3.3V, VO=1.8V AT 4A
EN VO
VO
FIGURE 19. ENABLE
FIGURE 20. DISABLE
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EL7563 Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
VIN=3.3V, VO=1.8V, IO=4A TO SHORT
IO
VO
FIGURE 21. SHORT-CIRCUIT PROTECTION
Block Diagram
0.1F 390pF
VREF VTJ 2.2nF CONTROLLER SUPPLY 22 VDD JUNCTION TEMPERATURE VOLTAGE REFERENCE
COSC D2 OSCILLATOR VDRV 0.22F D4
VHI VIN D1 D3
3.3V
0.22F
PWM CONTROLLER
POWER FET DRIVERS POWER FET
0.22F 4.7H
0.1F VOUT (2.5V, 4A)
330F PGND
1.58k 1k
2.2nF
EN STP STN POWER TRACKING
CURRENT SENSE VREF
+
PG
SGND
FB
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FN7296.2 May 13, 2005
EL7563 Applications Information
Circuit Description General
The EL7563 is a fixed frequency, current mode controlled DC/DC converter with integrated N-channel power MOSFETs and a high precision reference. The device incorporates all the active circuitry required to implement a cost effective, user-programmable 4A synchronous stepdown regulator suitable for use in DSP core power supplies. By combining fused-lead packaging technology with an efficient synchronous switching architecture, high power output (10W) can be realized without the use of discrete external heat sinks. feedback is measured by the patented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conducting. At the beginning of each oscillator period the high-side NMOS switch is turned on. The comparator inputs are gated off for a minimum period of time of about 150ns (LEB) after the high-side switch is turned on to allow the system to settle. The Leading Edge Blanking (LEB) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. If the inductor current exceeds the maximum current limit (ILMAX) a secondary over-current comparator will terminate the high-side switch on time. If ILMAX has not been reached, the feedback voltage FB derived from the regulator output voltage VOUT is then compared to the internal feedback reference voltage. The resultant error voltage is summed with the current feedback and slope compensation ramp. The high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. However, the maximum on-duty ratio of the high-side switch is limited to 95%. In order to eliminate cross-conduction of the high-side and low-side switches a 15ns break-beforemake delay is incorporated in the switch drive circuitry. The output enable (EN) input allows the regulator output to be disabled by an external logic control signal.
PWM Controller
The EL7563 regulates output voltage through the use of current-mode controlled pulse width modulation. The three main elements in a PWM controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modulator output. In a step-down (buck) converter, the feedback loop forces the time-averaged output of the modulator to equal the desired output voltage. Unlike pure voltage-mode control systems, current-mode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output voltage by adjusting the PWM duty-cycle in response to changes in line or load conditions. Since the output voltage is equal to the time-averaged of the modulator output, the relatively large LC time constant found in power supply applications generally results in low bandwidth and poor transient response. By directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely limited by the output LC filter and can react more quickly to changes in line and load conditions. This feedforward characteristic also simplifies AC loop compensation since it adds a zero to the overall loop response. Through proper selection of the current-feedback to voltage-feedback ratio the overall loop response will approach a one-pole system. The resulting system offers several advantages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response. The heart of the controller is an input direct summing comparator which sum voltage feedback, current feedback, slope compensation ramp and power tracking signals together. Slope compensation is required to prevent system instability that occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the overall system. The slope compensation is fixed internally and optimized for 500mA inductor ripple current. The power tracking will not contribute any input to the comparator steady-state operation. Current
Output Voltage Setting
In general:
R 2 V OUT = 0.992V x 1 + ------ R 1
However, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loopgain is changed. This is shown in the performance curves. A 100nA pull-up current from FB to VDD forces VOUT to GND in the event that FB is floating.
NMOS Power FETs and Drive Circuitry
The EL7563 integrates low on-resistance (30m) NMOS FETs to achieve high efficiency at 4A. In order to use an NMOS switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (LX). This is accomplished by bootstrapping the VHI pin above the LX voltage with an external capacitor CVHI and internal switch and diode. When the low-side switch is turned on and the LX voltage is close to GND potential, capacitor CVHI is charged through internal switch to VDRV, typically 6V with external charge-pump. At the beginning of the next cycle the highside switch turns on and the LX pins begin to rise from GND to VIN potential. As the LX pin rises the positive plate of capacitor CVHI follows and eventually reaches a value of VDRV+VIN, typically 9V, for VIN=3.3V. This voltage is then level shifted and used to drive the gate of the high-side FET, via the VHI pin. A value of 0.22F for CVHI is recommended.
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EL7563
Reference
A 1.5% temperature compensated bandgap reference is integrated in the EL7563. The external VREF capacitor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. A value of 0.1F is recommended.
Junction Temperature Sensor
An internal temperature sensor continuously monitors die temperature. In the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. The upper and low trip-points are set to 135C and 115C respectively. The VTJ pin is an accurate indication of the internal silicon junction temperature (see performance curve.) The junction temperature TJ (C) can be deducted from the following relation:
T J = 75 + 1.2 - VTJ ------------------------0.00384
Oscillator
The system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 95%. Operating frequency can be adjusted through the COSC pin or can be driven by an external source. If the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. Since CSLOPE value is derived from the COSC ramp, changes to COSC ramp will change the CSLOPE compensation ramp which determine the open-loop gain of the system. When external synchronization is required, always choose COSC such that the free-running frequency is at least 20% lower than that of sync source to accommodate component and temperature variations. Figure 22 shows a typical connection.
1 2 3 390pF 5 6 7 8 9 10 EL7563 20 19 18 16 15 14 13 12 11
Where VTJ is the voltage at VTJ pin in volts.
Power Good and Power On Reset
During power up the output regulator will be disabled until VIN reaches a value of approximately 2.9V. About 300mV hysteresis is present to eliminate noise-induced oscillations. Under-voltage and over-voltage conditions on the regulator output are detected through an internal window comparator. A logic high on the PG output indicates that the regulated output voltage is within about +10% of the nominal selected output voltage.
100pF EXTERNAL OSCILLATOR
BAT54S
FIGURE 22. OSCILLATOR SYNCHRONIZATION
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FN7296.2 May 13, 2005
EL7563
Power Tracking
The power tracking pins STP and STN are the inputs to a comparator, whose HI output forces the PWM controller to skip switching cycle.
2. Offset Tracking
The intended start-up sequence is shown in Figure 24. In this configuration, VC will not start until VP reaches a preset value of:
RB --------------------- x V IN RA + RB
1. Linear Tracking
In this application, it is always the case that the lower voltage supply VC tracks the higher output supply VP. See Figure 23.
1 2 6 7 8 9 10
+ -
20 19 15 EL7563 14 13 12 11 VOUT VP VC
VC
1 2 6 7 8 9 10
+ -
20 TIME 19 15 EL7563 14 13 12 11 VP
FIGURE 23. LINEAR POWER TRACKING
1 2 6 VIN RA 7 8 9 RB 10 STP
+ STN -
20 19 15 EL7563 14 13 12 11 VOUT VP VC
VC
1 2 6 7 8 9 10 STP
+ STN -
20 TIME 19 15 EL7563 14 13 12 11 VP
FIGURE 24. OFFSET POWER TRACKING
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EL7563
The second way of offset tracking is to use the EN and Power Good pins, as shown in Figure 25. In this configuration, VP does not have to be larger than VC.
3. External Soft Start
An external soft start can be combined with auxiliary supply tracking to provide desired soft start other than internally preset soft start (Figure 26). The appropriate start-up time is:
VO t s = R x C x --------V IN
1 2 3 5 6 7 8 9 10 EL7563
EN 20 19 PG 18 16 15 14 13 12 11 VP VC VC
1 2 3 5 6 7 8 9 10 EL7563
EN 20 19 PG 18 16 15 14 13 12 11 VP TIME
FIGURE 25. OFFSET TRACKING
1 2 6 VIN 7 R 8 9 10 C STP STN
+ -
20 19 15 EL7563 14 13 12 11 VOUT
FIGURE 26. EXTERNAL SOFT START
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FN7296.2 May 13, 2005
EL7563
Start-up Delay
A capacitor can be added to the EN pin to delay the converter start-up (Figure 27) by utilizing the pull-up current. The delay time is approximately:
t d ( ms ) = 1200 x C ( F )
Thermal Management
The EL7563CM utilizes "fused lead" packaging technology in conjunction with the system board layout to achieve a lower thermal resistance than typically found in standard SO20 packages. By fusing (or connecting) multiple external leads to the die substrate within the package, a very conductive heat path is created to the outside of the package. This conductive heat path MUST then be connected to a heat sinking area on the PCB in order to dissipate heat out and away from the device. The conductive paths for the SO20 package are the fused leads: # 6, 7, 11, 12, and 13. If a sufficient amount of PCB metal area is connected to the fused package leads, a junction-to-ambient resistance of 43C/W can be achieved (compared to 85C/W for a standard SO20 package). The general relationship between PCB heat-sinking metal area and the thermal resistance for this package is shown in the Performance Curves section of this data sheet. It can be readily seen that the thermal resistance for this package approaches an asymptotic value of approximately 43C/W without any airflow, and 33C/W with 100 LFPM airflow. Additional information can be found in Application Note #8 (Measuring the Thermal Resistance of Power Surface-Mount Packages). For a thermal shutdown die junction temperature of 135C, and power dissipation of 1.5W, the ambient temperature can be as high as 70C without airflow. With 100 LFPM airflow, the ambient temperature can be extended to 85C.
The EL7563CRE utilizes the 28-pin HTSSOP package. The majority of heat is dissipated through the heat pad exposed at the bottom of the package. Therefore, the heat pad needs to be soldered to the PCB. The thermal resistance for this package is as low as 29C/W, better than that of the SO20. Typical performance is shown in the curve section. The actual junction temperature can be measured at VTJ pin. Since the thermal performance of the IC is heavily dependent on the board layout, the system designer should exercise care during the design phase to ensure that the IC will operate under the worst-case environmental conditions.
Layout Considerations
The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor.) The trace connected to the FB pin is the most sensitive trace. It needs to be as short as possible and in a "quiet" place, preferably between PGND or SGND traces. In addition, the bypass capacitor connected to the VDD pin needs to be as close to the pin as possible. The heat of the chip is mainly dissipated through the PGND pins and through the heat pad at the bottom of the CRE package. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance. The demo board is a good example of layout based on these principles. Please refer to the EL7563 Application Brief for the layout.
1 2 6 7 8 9 10 STP
+ STN -
20 C 19 15 EL7563 14 13 12 11 TIME td VIN VO VOUT
FIGURE 27. START-UP DELAY
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FN7296.2 May 13, 2005
EL7563 SO Package Outline Drawing
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FN7296.2 May 13, 2005
EL7563 HTSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7296.2 May 13, 2005

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